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The paper presents the discussion of ways of implementation in hardware of a vehicle detection algorithm. Efficiency and speed of operation are the basic criteria for judging its usefulness for application in road traffic control systems. Instruction set architectures and configurable processing architectures are assessed for the demanding video stream calculation tasks. The significance of decomposition of the detection algorithm for achieving set forth efficiency and speed requirements is presented.
The vehicle detection algorithm is based on extracting moving objects on a slowly changing background. Updating a background template and determining vehicle presence are the main tasks. The algorithm may be divided into data driven computation blocks. It is shown that a processing pipeline, designed using reconfigurable FPGA resources, satisfies implementation criteria providing a robust solution for application in road traffic control systems.
Keywords: image processing, processing architectures, vehicle detection